This invention relates to a semiconductor package for multi-chip and three-dimensional configurations and a method of making the same.
Packaging is the process in which semiconductor is enclosed for protection and to provide ease of handling and usage. Common techniques for enclosing semiconductor include encapsulation and glob-top. In both of these methods, the semiconductor is covered with a polymer, which, however, has the side effects of trapping heat and raising the stress within the package. In certain cases, the stress within the package can be sufficient to crack the semiconductor or give rise to delaminations at various locations within the package. In addition, the trapped heat can cause thermally induced failures.
Thus, most packaging technologies seek to accomplish a high heat transfer rate while minimizing the stress that can build up internally. This is particularly important as the trend for miniaturization further pushes the level of integration for many semiconductors and has increased the demand on heat removal and space usage.
One way to increase the heat transfer from the semiconductor is by directly mounting it onto a metallic heat-spreader. The TBGA and the superBGA packages are popular configurations that seek to employ this concept. Others have sought to improve on the space requirement of these two packages by proposing to stack them on top of each other so as to produce a three-dimensional structure. As the TBGA, superBGA and other similar packages require a rigid heat-spreader, a high stress level can be generated within the packages.
A semiconductor package includes a thin, flexible metallic foil as a heat spreader and/or a grounding/electrical plane. The thin, flexible metallic foil may be etched, stamped, formed, or generally processed to yield circuitry patterns. The foil is also folded to yield an indentation, which can be formed through a number of techniques whether mechanical or chemical, and its shape can be rectangular or otherwise.
In one general aspect, circuitries are attached to either one or both sides of the foil. Such circuitries are well known in the art and can take the forms of a polyamide tape with metallization, a BT resin with metallization, or any other similar forms. There are also numerous ways to form these circuitries together with the foil as a single substrate. Some examples of these methods are disclosed herein, although this invention is not confined to those examples.
Electrically conductive paths can also be formed between the circuitries on the two sides of the foil, as discussed later. In one implementation, electronic devices, whether in packaged or unpackaged form, are mechanically, chemically, and/or electrically attached to the inside of the indentation and/or to the other side of the substrate. Such electronic devices are then covered using a polymer for protection. Such covering process is well known in the art and can take the form of a glob-top, encapsulation, or similar processes. Part of the foil can be exposed during the polymer covering process. Such exposed foil serves to provide a heat path.
In one implementation, the subject package functions as a Multi-Chip-Module (MCM). In yet another implementation, numerous MCM""s are electrically and/or mechanically connected on top of one another in a three-dimensional stacked up structure. The electrical connections are made possible by electrically conductive paths formed into the polymer covering and the conduction paths formed between the circuitries on the two sides of the foil.
In another general aspect, a semiconductor package includes a metallic foil, a substrate, a stiffener, and a semiconductor element. The metallic foil has a front surface and a rear surface and is formed to have a recess portion including a bottom and an extended border region around the recess portion. The substrate is attached to the front surface of the foil over the border region to provide a support for electrical connection of a semiconductor element. The substrate has an opening exposing the recess portion. The stiffener is formed on the rear surface of the foil for enhancing the rigidity of the foil. The stiffener extends over the border region and around the recess portion, with the rear surface of the bottom of the recess portion exposed for heat dissipation. The semiconductor element is mounted on the bottom of and within the recess portion. The foil may have a material thickness less than 1 mm or in the range of 0.5 mm to 0.9 mm. The stiffener may include a polymer-based material.
In one implementation, the stiffener substantially fully occupies the space on the rear side of the border region and has an outer surface lying substantially flush with the rear surface of the bottom of the recess portion. The substrate may include a polyamide-based material or a BT based material. The substrate may be provided on at least its outer surface with a conductive layer in the form of a plurality of metal patterns for electrical connection of the semiconductor element. The conductive layer may be provided with a plurality of contact balls. The substrate may include at least one grounding via which extends through the substrate and has one end in contact with the foil. The foil and substrate may be formed in a single operation as a one-piece structure.
The semiconductor package may include a polymer filling the recess portion of the foil to enclose the semiconductor element and cover a rim portion of the opening of the substrate. The border region of the foil may be formed with at least one aperture, and an additional semiconductor element may be mounted on a rear surface of the substrate through the aperture and enclosed by the stiffener. The substrate may be provided on its outer surface with a conductive layer for electrical connection of the first-mentioned semiconductor element and on its inner surface with another conductive layer for electrical connection of the additional semiconductor element. The stiffener may include a plurality of conductive vias extending through it. In this case, the package may be stackable with another said semiconductor package to form a multi-layer package arrangement, with the conductive vias enabling grounding and/or thermal conduction between the metallic foils of the packages.
A multi-layer semiconductor package may be formed by at least two semiconductor packages, in which adjacent packages are interconnected by solder.
According to another aspect, a method of making a semiconductor package includes providing a metallic foil having a front surface and a rear surface, forming the foil to have a recess portion including a bottom and an extended border region around the recess portion, attaching a substrate to the front surface of the foil over the border region to provide a support for electrical connection of a semiconductor element, forming a stiffener on the rear surface of the foil to enhance the rigidity of the foil. The substrate has an opening to expose the recess portion and the stiffener extends over the border region and around the recess portion. The rear surface of the bottom of the recess portion is exposed for heat dissipation, and a semiconductor element is mounted on the bottom of and within the recess portion.
Forming the stiffener may include arranging the stiffener to substantially fully occupy the space on the rear side of the border region and to have an outer surface lying substantially flush with the rear surface of the bottom of the recess portion.
The method may include providing the substrate on at least its outer surface with a conductive layer in the form of a plurality of metal patterns for electrical connection of the semiconductor element. Forming the foil and attaching the substrate may be performed in a single operation to form the foil and substrate as a one-piece structure.
The method may include filling the recess portion of the foil with a polymer to enclose the semiconductor element and cover a rim portion of the opening of the substrate. The method may include forming at least one aperture in the border region of the foil, and mounting an additional semiconductor element on a rear surface of the substrate through the aperture. The method may further include providing the substrate on its outer surface with a conductive layer for electrical connection of the first-mentioned semiconductor element and on its inner surface with another conductive layer for electrical connection of the additional semiconductor element.
The method may include stacking at least the two semiconductor packages one on top of the other to form a multi-layer package arrangement, and providing grounding and/or thermal conductive paths between the metallic foils of adjacent packages. The method may include interconnecting adjacent packages by solder.
The semiconductor package offers a high thermal dissipation capability while maintaining a high degree of flexibility in semiconductor packaging, as well as the ability to accommodate a multitude of electronic devices and/or a three-dimensional stacking structure. The semiconductor package may function as a Multi-Chip-Module (MCM) thereby enabling an efficient utilization of physical geometry. Additionally, multiple packages (whether in single-chip and/or multi-chip configuration) may be functionally and/or mechanically stacked up together, thereby enabling a further more efficient usage of board space.
Other features and advantages will be apparent from the description, the drawings, and the claims.